1. Field of the Invention
The present invention relates to a pseudo random pattern generation circuit, and more specifically to a pseudo random pattern generation circuit incorporated in a LSI (large scale integrated circuit) chip and capable of generating a test pattern which is used for checking an operation of an internal circuit within the LSI chip.
2. Description of Related Art
In the prior art, this type of pseudo random pattern generation circuits have been configured to have a normal input operation mode functioning as a buffer outputting a received input data without modification, a boundary scan mode for checking only wirings between internal circuits of the LSI chip, and a pseudo random pattern generation mode for an inherent test pattern.
For example, a typical conventional pseudo random pattern generation circuit of four bits have been comprised of four flipflops, four selectors controlled by operation mode signals so as to supply a signal to an input of the four flipflops, respectively, and an exclusive-OR gate receiving an output of selected ones of the four flipflops and outputting an signal to the selector of the most significant bit.
In the normal input operation mode, four input bits are selected by the four selectors, respectively, and outputted without modification so as to latched by the four flipflops, respectively, so that the four input bits are supplied as output data to an internal circuit of the LSI chip.
In the boundary scan mode, a data signal outputted from an adjacent boundary scan buffer is inputted through the selector of the most significant bit to the associated flipflop of the most significant bit, whose output is supplied through the selector of the second most significant bit to the associated flipflop of the second most significant bit. An output of the flipflop of the second most significant bit is supplied through the selector of the third most significant bit to the associated flipflop of the third most significant bit, whose output is supplied through the selector of the least significant bit to the associated flipflop of the least most significant bit. An output of the associated flipflop of the least most significant bit is supplied as an shifted-out data to another adjacent internal circuit of the LSI chip.
In the pseudo random pattern generation mode, the circuit operates similarly to the boundary scan mode, except that, in place of the data signal outputted from an adjacent boundary scan buffer, an output of the exclusive-OR gate is supplied through the selector of the most significant bit to the associated flipflop of the most significant bit, and the outputs of the four flipflops are outputted as the output data. Therefore, the selector of the most significant bit is of a three-input type, while the other selector is of a two-input type.
In the above mentioned pseudo random pattern generation circuit as mentioned above, when the data shifted through the flipflops in the boundary scan mode is shifted out from the circuit, the outputs of all the flipflops are outputted as the output data to the internal circuit of the LSI chip, with the result that the internal circuit is caused to operate. Because of this, the preceding internal condition cannot be maintained in the LSI chip, and therefore, after the checking, when the operation is returned to the normal operation mode, the operation is confused.
In addition, in the normal input operation mode, since the input data is transferred through the selector and the flipflop, a delay of one clock cycle occurs until the input data is outputted to the internal circuit of the LSI chip, and therefore, the processing speed lowers.